Invention Grant
- Patent Title: CMOS structure having low resistance contacts and fabrication method
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Application No.: US14189509Application Date: 2014-02-25
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Publication No.: US10546856B2Publication Date: 2020-01-28
- Inventor: Qing Liu , Xiuyu Cai , Chun-chen Yeh , Ruilong Xie
- Applicant: STMICROELECTRONICS, INC. , GLOBALFOUNDRIES INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US TX Coppell KY Grand Cayman US NY Armonk
- Assignee: STMICROELECTRONICS, INC.,GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: STMICROELECTRONICS, INC.,GLOBALFOUNDRIES INC.,INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US TX Coppell KY Grand Cayman US NY Armonk
- Agency: Seed IP Law Group LLP
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8238 ; H01L21/285 ; H01L21/768 ; H01L23/485 ; H01L29/45
Abstract:
A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.
Public/Granted literature
- US20150243660A1 CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD Public/Granted day:2015-08-27
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