Invention Grant
- Patent Title: Detection of double bit errors and correction of single bit errors in a multiword array
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Application No.: US15984108Application Date: 2018-05-18
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Publication No.: US10552260B2Publication Date: 2020-02-04
- Inventor: Rahul Gawde , Michael A. Kost , Alvin C. Storvik
- Applicant: Cirrus Logic International Semiconductor Ltd.
- Applicant Address: US TX Austin
- Assignee: Cirrus Logic, Inc.
- Current Assignee: Cirrus Logic, Inc.
- Current Assignee Address: US TX Austin
- Agency: Jackson Walker L.L.P.
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H03M13/15 ; G11C29/52 ; H03M13/19 ; H03M13/29

Abstract:
An error correction code for an array of N words of M bits each may be generated by: (i) for each word of the N words, computing a respective set of checkbits for single-error correction of such word; (ii) computing a set of bit-position-related checkbits comprising a bitwise logical exclusive OR of all of the sets of checkbits for single-error correction of the N words; (iii) for each word of the N words, computing a respective parity for the respective set of checkbits and the word itself in order to form a vector of N parity bits; (iv) computing a set of word-related checkbits for single-error correction of the vector of N parity bits; and (v) computing a cumulative parity bit comprising a parity calculation of the set of bit-position-related checkbits, the set of word-related checkbits, and the vector of N parity bits.
Public/Granted literature
- US20180357124A1 DETECTION OF DOUBLE BIT ERRORS AND CORRECTION OF SINGLE BIT ERRORS IN A MULTIWORD ARRAY Public/Granted day:2018-12-13
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