Invention Grant
- Patent Title: Automated redesign of integrated circuits using relaxed spacing rules
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Application No.: US15873225Application Date: 2018-01-17
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Publication No.: US10552567B2Publication Date: 2020-02-04
- Inventor: Deniz E. Civay , Elise Laffosse
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Gibb & Riley, LLC
- Agent David A. Cain, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F7/20 ; H01L27/02 ; H01L23/522

Abstract:
Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).
Public/Granted literature
- US20190220567A1 AUTOMATED REDESIGN OF INTEGRATED CIRCUITS USING RELAXED SPACING RULES Public/Granted day:2019-07-18
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