公开(公告)号：US20170141027A1

公开(公告)日：2017-05-18

申请号：US14939365

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erik R. Hosler ,  Deniz E. Civay

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US20190220567A1

公开(公告)日：2019-07-18

申请号：US15873225

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deniz E. Civay ,  Elise Laffosse

IPC: G06F17/50 ,  H01L27/02 ,  G03F7/20

Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

公开(公告)号：US09704807B2

公开(公告)日：2017-07-11

申请号：US14939251

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deniz E. Civay ,  Erik R. Hosler

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5328 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US09941301B1

公开(公告)日：2018-04-10

申请号：US15388772

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4916 ,  H01L29/7838

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US09633942B1

公开(公告)日：2017-04-25

申请号：US14939365

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erik R. Hosler ,  Deniz E. Civay

IPC: H01L21/311 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76823 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US10186524B2

公开(公告)日：2019-01-22

申请号：US15912141

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： David Pritchard ,  Lixia Lei ,  Deniz E. Civay ,  Scott D. Luning ,  Neha Nayyar

IPC: H01L27/12 ,  H01L29/49 ,  H01L21/84 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234

Abstract: Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.

公开(公告)号：US09754829B2

公开(公告)日：2017-09-05

申请号：US14939464

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erik R. Hosler ,  Deniz E. Civay

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76823 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US09748176B2

公开(公告)日：2017-08-29

申请号：US14939319

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Deniz E. Civay ,  Erik R. Hosler

IPC: H01L21/322 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5328 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US20170140985A1

公开(公告)日：2017-05-18

申请号：US14939464

申请日：2015-11-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Erik R. Hosler ,  Deniz E. Civay

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76823 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

公开(公告)号：US10552567B2

公开(公告)日：2020-02-04

申请号：US15873225

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deniz E. Civay ,  Elise Laffosse

IPC: G06F17/50 ,  G03F7/20 ,  H01L27/02 ,  H01L23/522

Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).