公开(公告)号：US20190220567A1

公开(公告)日：2019-07-18

申请号：US15873225

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deniz E. Civay ,  Elise Laffosse

IPC: G06F17/50 ,  H01L27/02 ,  G03F7/20

Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

公开(公告)号：US10552567B2

公开(公告)日：2020-02-04

申请号：US15873225

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Deniz E. Civay ,  Elise Laffosse

IPC: G06F17/50 ,  G03F7/20 ,  H01L27/02 ,  H01L23/522

Abstract: Methods and systems access an original integrated circuit (IC) design. The smallest spacing between elements in the original IC design is an “original” minimum spacing. These methods and systems automatically convert the original IC design to a reduced IC design, and the smallest spacing between elements in the reduced IC design is a “reduced” minimum spacing that is less than the original minimum spacing. Such methods and systems either automatically replace a single via in the original IC design with multiple vias in the reduced IC design (in an area where the single via was located in the original IC design) or automatically replace the single via in the original IC design with a via bar in the reduced IC design (in an area where the single via was located in the original IC design).

公开(公告)号：US09576097B1

公开(公告)日：2017-02-21

申请号：US14930949

申请日：2015-11-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elise Laffosse ,  Deniz Elizabeth Civay

IPC: H01L21/311 ,  G06F17/50 ,  H01L21/768

CPC classification number: H01L21/76816 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/76807 ,  Y02P90/265

Abstract: Methods and computer program products for decomposing and etching a circuit pattern layout are provided. The methods may include decomposing a circuit pattern layout into a first sub-pattern and second sub-pattern, where the decomposing includes: identifying, from the circuit pattern layout, a design line and a design via location associated with the design line; forming a first pattern line for the first sub-pattern corresponding to a first portion of the design line, and a second pattern line for the second sub-pattern corresponding to a second portion of the design line, with the first and second pattern lines overlapping at the design via location in an overlay of the first sub-pattern with the second sub-pattern. The first sub-pattern may be etched in a first circuit structure layer and the second sub-pattern etched in a second circuit structure layer, the etching at least partially forming a via at the design via location.

Abstract translation: 提供了用于分解和蚀刻电路图案布局的方法和计算机程序产品。 所述方法可以包括将电路图案布局分解为第一子图案和第二子图案，其中分解包括：通过与设计线相关联的位置从电路图案布局识别设计线和设计; 形成对应于设计线的第一部分的第一子图案的第一图案线和对应于设计线的第二部分的第二子图案的第二图案线，其中第一和第二图案线重叠 在通过第一子图案与第二子图案的重叠的位置处的设计。 可以在第一电路结构层中蚀刻第一子图案，并且在第二电路结构层中蚀刻第二子图案，蚀刻至少部分地在设计经过位置形成通孔。