A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.