公开(公告)号：US20170116945A1

公开(公告)日：2017-04-27

申请号：US15299592

申请日：2016-10-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Seungwan Cho ,  Seungho Heo

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G02F1/133308 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/061

Abstract: A display device includes a display panel and a shift register generating a gate pulse and sequentially outputting the gate pulse to gate lines in response to a voltage at a Q node of each of dependently connected stages. An nth (n is a natural number) stage of the shift register includes a pull-up transistor, a start controller, a reset controller, and a first reset output terminal controller. A first reset output controller outputs a reset signal to a reset signal output terminal at a timing at which a second clock signal and a first output control signal output in a non-display period are synchronized.

公开(公告)号：US20140152935A1

公开(公告)日：2014-06-05

申请号：US14082022

申请日：2013-11-15

Applicant: LG Display Co., Ltd.

Inventor： Seungho Heo ,  Byeongseong So

IPC: G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/13454 ,  G02F1/1339 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2202/16

Abstract: The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Abstract translation: 本公开涉及减少包括具有围绕显示区域的非显示区域的基板的平面显示面板的边框区域，所述显示区域包括耦合到相应行像素的公共线; 以及形成在非显示区域中的栅极驱动器。 显示器还可以包括形成在非显示区域中并被配置为提供公共线电压的导电密封区域; 以及多个公共焊盘，其形成在导电密封区域内并且各自耦合到对应的一条公共线，以将公共线电压施加到像素行。 或者，显示器还可以包括形成在栅极驱动器和显示区域之间的非显示区域中的垂直公共线，垂直公共线从非显示区域的顶部延伸到底部并且耦合到所述公共线以应用 一个共同的电压。

公开(公告)号：US11839109B2

公开(公告)日：2023-12-05

申请号：US17524645

申请日：2021-11-11

Applicant: LG Display Co., Ltd.

Inventor： Seungho Heo ,  Beong-Ho Lee ,  Sangdeok Ha ,  JeongGi Yun

IPC: H01L21/00 ,  H10K59/121 ,  H10K59/35 ,  H10K59/122

CPC classification number: H10K59/121 ,  H10K59/352 ,  H10K59/122

Abstract: According to an aspect of the present disclosure, a display apparatus includes a substrate in which a plurality of sub pixels is defined; a plurality of light emitting diodes which are disposed in the plurality of sub pixels, share a common organic layer and a cathode, and have an emission layer and an anode which are separated, respectively; a conductive layer disposed between the plurality of sub pixels; and a bank which is disposed below the cathode between the plurality of light emitting diodes and exposes the anode and the conductive layer. The plurality of sub pixels include a first sub pixel and a second sub pixel having a turn-on voltage lower than that of the first sub pixel, and the conductive layer is disposed to be closer to the second sub pixel between the first sub pixel and the second sub pixel.

公开(公告)号：US10217426B2

公开(公告)日：2019-02-26

申请号：US15299592

申请日：2016-10-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Seungwan Cho ,  Seungho Heo

IPC: G09G3/36 ,  G02F1/1333

Abstract: A display device includes a display panel and a shift register generating a gate pulse and sequentially outputting the gate pulse to gate lines in response to a voltage at a Q node of each of dependently connected stages. An nth (n is a natural number) stage of the shift register includes a pull-up transistor, a start controller, a reset controller, and a first reset output terminal controller. A first reset output controller outputs a reset signal to a reset signal output terminal at a timing at which a second clock signal and a first output control signal output in a non-display period are synchronized.

公开(公告)号：US10553147B2

公开(公告)日：2020-02-04

申请号：US15718804

申请日：2017-09-28

Applicant: LG DISPLAY CO., LTD.

Inventor： Hyunguk Jang ,  Seungho Heo

IPC: G11C19/00 ,  G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: A display device comprises a pixel array, a timing controller, a Q node control signal input line, and a shift register. In the pixel array, data lines and gate lines are defined, and pixels are arranged in a matrix. The timing controller outputs a start signal and a first reset signal. The Q node control signal input line receives the start signal and the first reset signal. The shift register comprises a plurality of stages connected as a cascade, and sequentially supplies dummy gate pulses or gate pulses applied to the gate lines.

公开(公告)号：US09818353B2

公开(公告)日：2017-11-14

申请号：US14733220

申请日：2015-06-08

Applicant: LG DISPLAY CO., LTD.

Inventor： Byeongseong So ,  Seungho Heo

IPC: G09G3/36 ,  G09G3/32 ,  G09G3/20

CPC classification number: G09G3/3611 ,  G09G3/20 ,  G09G3/3677 ,  G09G2230/00 ,  G09G2310/0218 ,  G09G2310/0267 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2320/0223

Abstract: Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.

公开(公告)号：US09436049B2

公开(公告)日：2016-09-06

申请号：US14082022

申请日：2013-11-15

Applicant: LG Display Co., Ltd.

Inventor： Seungho Heo ,  Byeongseong So

IPC: G02F1/1362 ,  G02F1/1345 ,  G02F1/1339 ,  G02F1/1343

CPC classification number: G02F1/13454 ,  G02F1/1339 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2202/16

Abstract: The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Abstract translation: 本公开涉及减少包括具有围绕显示区域的非显示区域的基板的平面显示面板的边框区域，所述显示区域包括耦合到相应行像素的公共线; 以及形成在非显示区域中的栅极驱动器。 显示器还可以包括形成在非显示区域中并被配置为提供公共线电压的导电密封区域; 以及多个公共焊盘，其形成在导电密封区域内并且各自耦合到对应的一条公共线，以将公共线电压施加到像素行。 或者，显示器还可以包括形成在栅极驱动器和显示区域之间的非显示区域中的垂直公共线，垂直公共线从非显示区域的顶部延伸到底部并且耦合到所述公共线以应用 一个共同的电压。