Invention Grant
- Patent Title: Multi-layer leadless semiconductor package and method of manufacturing the same
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Application No.: US15788753Application Date: 2017-10-19
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Publication No.: US10573590B2Publication Date: 2020-02-25
- Inventor: Antonio Bambalan Dimaano, Jr. , Roel Adeva Robles
- Applicant: UTAC Headquarters Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: UTAC Headquarters Pte. Ltd.
- Current Assignee: UTAC Headquarters Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Horizon IP Pte Ltd.
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/683 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/00

Abstract:
Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.
Public/Granted literature
- US20180114749A1 MULTI-LAYER LEADLESS SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-04-26
Information query
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