公开(公告)号：US09564387B2

公开(公告)日：2017-02-07

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US10658277B2

公开(公告)日：2020-05-19

申请号：US16057792

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Nataporn Charusabha ,  Saravuth Sirinorakul ,  Preecha Joymak ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/433

Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

公开(公告)号：US10573590B2

公开(公告)日：2020-02-25

申请号：US15788753

申请日：2017-10-19

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Roel Adeva Robles

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.

公开(公告)号：US10714431B2

公开(公告)日：2020-07-14

申请号：US16057773

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Dzafir Bin Mohd Shariff ,  Seung Guen Park ,  Roel Adeva Robles

IPC: H01L23/552 ,  H01L23/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package.

公开(公告)号：US20160064310A1

公开(公告)日：2016-03-03

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/66 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。