公开(公告)号：US09508623B2

公开(公告)日：2016-11-29

申请号：US14731484

申请日：2015-06-05

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/00 ,  H01L23/544

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

Abstract translation: 公开了用于形成半导体封装的半导体封装和方法。 该方法包括提供具有第一和第二主表面的晶片。 晶片由多个管芯和设置在晶片的第一主表面上的多个外部电触点制成。 该方法包括处理晶片。 处理晶片包括将晶片分离成多个单独的芯片。 单个管芯包括第一和第二主表面以及第一和第二侧壁，并且外部电触头形成在管芯的第一主表面上。 形成密封剂材料。 密封剂材料覆盖模具的第一和第二侧壁的至少一部分。

公开(公告)号：US10354934B2

公开(公告)日：2019-07-16

申请号：US15961839

申请日：2018-04-24

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/28 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US20240055292A1

公开(公告)日：2024-02-15

申请号：US18448667

申请日：2023-08-11

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Roel Adeva Robles ,  Chee Kay Chow

IPC: H01L21/683

CPC classification number: H01L21/6836 ,  H01L2221/68354 ,  H01L2221/68309 ,  H01L2221/68318

Abstract: A first carrier has a first plate. A tape is disposed on the first plate. A second plate is disposed over the first plate. The second plate has a trench aligned to the tape and an opening formed through the second plate over the tape. A singulated semiconductor package is disposed on the tape in the opening of the second plate. A second carrier has a static datum and a movable datum. The movable datum is moved toward the static datum. An aperture substrate is disposed around the static datum and movable datum. A manufacturing process is performed on the aperture substrate.

公开(公告)号：US10714431B2

公开(公告)日：2020-07-14

申请号：US16057773

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Dzafir Bin Mohd Shariff ,  Seung Guen Park ,  Roel Adeva Robles

IPC: H01L23/552 ,  H01L23/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package.

公开(公告)号：US09978658B2

公开(公告)日：2018-05-22

申请号：US15361487

申请日：2016-11-27

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nathapong Suthiwongsunthorn ,  Antonio Jr. Bambalan Dimaano ,  Rui Huang ,  Hua Hong Tan ,  Kriangsak Sae Le ,  Beng Yeung Ho ,  Nelson Agbisit De Vera ,  Roel Adeva Robles ,  Wedanni Linsangan Micla

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3105 ,  H01L21/683 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2224/0391 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2924/1815 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.

公开(公告)号：US11901308B2

公开(公告)日：2024-02-13

申请号：US17382283

申请日：2021-07-21

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Il Kwon Shim ,  Kok Chuen Lock ,  Roel Adeva Robles ,  Eakkasit Dumsong

IPC: H01L23/552 ,  H01L23/36 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49503 ,  H01L24/32 ,  H01L2224/32245

Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.

公开(公告)号：US11227818B2

公开(公告)日：2022-01-18

申请号：US16942715

申请日：2020-07-29

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Wing Keung Lam ,  Saravuth Sirinorakul ,  Kok Chuen Lock ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/48 ,  H01L21/00 ,  H01R9/00 ,  H05K7/00 ,  H05K7/18 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/16 ,  H01L23/00 ,  H01L23/498

Abstract: An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

公开(公告)号：US10658277B2

公开(公告)日：2020-05-19

申请号：US16057792

申请日：2018-08-07

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Nataporn Charusabha ,  Saravuth Sirinorakul ,  Preecha Joymak ,  Roel Adeva Robles

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L23/433

Abstract: Embodiments of the present invention are directed to a semiconductor package with improved thermal performance. The semiconductor package includes a package substrate comprising a top substrate surface and a bottom substrate surface. The package substrate comprises a thickness extending from the top substrate surface to the bottom substrate surface. A heat spreader is disposed on the top substrate surface. The heat spreader comprises a thickness extending from a top planar surface to a bottom planar surface of the heat spreader. The top planar surface of the heat spreader is defined with a die region and a non-die region surrounding the die region. A semiconductor die is directly disposed on the top planar surface of the heat spreader in the die region. The thickness of the heat spreader is greater relative to the thickness of the package substrate.

公开(公告)号：US10573590B2

公开(公告)日：2020-02-25

申请号：US15788753

申请日：2017-10-19

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Antonio Bambalan Dimaano, Jr. ,  Roel Adeva Robles

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Device and method of forming the device are disclosed. A device includes a buildup package substrate with top and bottom surfaces and a plurality of interlevel dielectric (ILD) layers with interconnect structures printed layer by layer and includes a die region and a non-die region on the top surface. A semiconductor die is disposed in the die and non-die regions of the package substrate and is electrically connected to the plurality of interconnect structures via a plurality of wire bonds. A plurality of conductive elements are disposed on the bottom surface of the package substrate and a dielectric layer encapsulates the semiconductor die, the wire bonds and the top surface of the buildup package substrate.