A circuit, where a first end of a resistive random access memory (RRAM) included in the circuit includes a first end of the circuit, and a second end of the RRAM is coupled to a first end of a first switch and a first end of a second switch, a second end of the first switch includes a second end of the circuit, and a first control end of the first switch and a second control end of the second switch are configured to make the first switch closed and the second switch open at the same time. Therefore, a working status of the RRAM is flexibly controlled.