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    Cabinet server and data center based on cabinet server
    3.
    发明授权
    Cabinet server and data center based on cabinet server 有权

    公开(公告)号：US10069189B2

    公开(公告)日：2018-09-04

    申请号：US15276207

    申请日：2016-09-26

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Shaojie Chen ,  Zhulin Wei ,  Junfeng Zhao ,  Rui He ,  Xiaowen Dong ,  Peng Lin ,  Wei Yang

    IPC: H01Q1/22 ,  G06F13/40 ,  H04W84/10

    Abstract: A cabinet server and a data center where the cabinet server includes multiple function node layers vertically arranged to form a server core and multiple intra-cabinet antennas vertically arranged and disposed at one side of the server core, an intra-cabinet antenna is wirelessly connected to adjacent intra-cabinet antennas. A transmission path is formed of the vertically arranged intra-cabinet antennas when a radio signal is transmitted within the cabinet server. Since the intra-cabinet antennas are disposed at the side of the server core, electromagnetic radiation generated by the radio signal in a transmission process has a relatively small effect on the function nodes, thereby reducing the effect of the electromagnetic radiation on various electronic devices in the function nodes, improving service lives of the electronic devices, and improving transmission quality of the radio signal.

    Data storage method and phase change memory
    4.
    发明授权
    Data storage method and phase change memory 有权

    公开(公告)号：US09899084B2

    公开(公告)日：2018-02-20

    申请号：US15412509

    申请日：2017-01-23

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Shujie Zhang

    IPC: G11C11/56 ,  G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/79

    Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

    Data Storage Method, Storage Apparatus, and Computing Device
    5.
    发明申请
    Data Storage Method, Storage Apparatus, and Computing Device 审中-公开
    数据存储方法，存储设备和计算设备

    公开(公告)号：US20170047119A1

    公开(公告)日：2017-02-16

    申请号：US15337710

    申请日：2016-10-28

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Jun Xu ,  Junfeng Zhao

    IPC: G11C14/00 ,  G11C7/10 ,  G06F12/128

    CPC classification number: G11C14/0045 ,  G06F12/0802 ,  G06F12/0868 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/205 ,  G11C7/1048 ,  G11C14/009

    Abstract: A data storage method, a storage apparatus and a computing device are disclosed. The method includes receiving a presetting command sent by a CPU, where the presetting command instructs to write 1 to a location, which corresponds to a cache line, in memory; writing, according to the presetting command, 1 to the location, which corresponds to the cache line, in the memory; receiving a write command sent by the CPU of writing data in the cache line to the memory; and writing, according to the write command, data 0 in the cache line to a location, which corresponds to the data 0, in the memory.

    Abstract translation: 公开了一种数据存储方法，存储装置和计算装置。 该方法包括接收由CPU发送的预设命令，其中预设命令指示将1写入与存储器中的高速缓存线对应的位置; 根据预置命令将1写入存储器中对应于高速缓存行的位置; 接收由CPU发送的写入命令，用于将高速缓存行中的数据写入存储器; 以及根据写入命令将高速缓存行中的数据0写入到存储器中对应于数据0的位置。

    Hybrid storage device, computer, control device, and power consumption reduction method
    7.
    发明授权
    Hybrid storage device, computer, control device, and power consumption reduction method 有权

    公开(公告)号：US10430096B2

    公开(公告)日：2019-10-01

    申请号：US15882683

    申请日：2018-01-29

    Applicant: Huawei Technologies Co., Ltd. ,  Fudan University

    Inventor： RenHua Yang ,  Junfeng Zhao ,  Wei Yang ,  Yinyin Lin

    IPC: G06F3/06 ,  G06F1/3234

    Abstract: A hybrid storage device includes a controller, a volatile storage unit, and a non-volatile storage unit. When the hybrid storage device is in a first working mode, the volatile storage unit is in an enabled state, and the non-volatile storage unit is in a disabled state; when the hybrid storage device is in a second working mode, the non-volatile storage unit is in an enabled state, and the volatile storage unit is in a disabled state. When the hybrid storage device runs in the first working mode, and when detecting that a running parameter of the computer meets a first switching condition, the controller enables the non-volatile storage unit, copies data in the volatile storage unit to the non-volatile storage unit, and switches the hybrid storage device to the second working mode.

    Memory activation method and apparatus, and memory controller
    9.
    发明授权
    Memory activation method and apparatus, and memory controller 有权

    公开(公告)号：US10127955B2

    公开(公告)日：2018-11-13

    申请号：US15607360

    申请日：2017-05-26

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Shihai Xiao ,  Wei Yang ,  Junfeng Zhao

    IPC: G11C8/10 ,  G11C8/16 ,  G06F3/06

    Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.

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