Invention Grant
- Patent Title: Method for analyzing design of an integrated circuit
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Application No.: US15957409Application Date: 2018-04-19
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Publication No.: US10592632B2Publication Date: 2020-03-17
- Inventor: Ryan Ryoung han Kim , Jae Uk Lee
- Applicant: IMEC VZW
- Applicant Address: BE Leuven
- Assignee: Imec vzw
- Current Assignee: Imec vzw
- Current Assignee Address: BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP17167587 20170421
- Main IPC: G06F17/00
- IPC: G06F17/00 ; G06T7/00 ; G06F17/50 ; G06N3/08 ; G03F7/20 ; G06F3/147

Abstract:
Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.
Public/Granted literature
- US20180307792A1 Method for Analyzing Design of an Integrated Circuit Public/Granted day:2018-10-25
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