公开(公告)号：US10147637B2

公开(公告)日：2018-12-04

申请号：US15889043

申请日：2018-02-05

Applicant: IMEC VZW

Inventor： Youssef Drissi ,  Ryan Ryoung han Kim ,  Stephane Lariviere ,  Praveen Raghavan ,  Darko Trivkovic

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.

公开(公告)号：US10978335B2

公开(公告)日：2021-04-13

申请号：US16563747

申请日：2019-09-06

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

公开(公告)号：US20190155138A1

公开(公告)日：2019-05-23

申请号：US16168234

申请日：2018-10-23

Applicant: IMEC VZW

Inventor： Jae Uk Lee ,  Ryan Ryoung han Kim

IPC: G03F1/22

Abstract: Example embodiments relate to masks for extreme-ultraviolet (extreme-UV) lithography and methods for manufacturing the same. An example embodiment includes a mask for extreme-UV lithography. The mask includes a substrate. The mask also includes a reflecting structure that is supported by the substrate in a use face and is reflection-effective for extreme-UV radiation impinging onto the reflecting structure from a side opposite the substrate. Further, the mask includes attenuating and phase-shifting portions that are distributed within the use face that are suitable for attenuating and phase-shifting extreme-UV radiation parts reflected by the mask through the portions such that an upper surface of the mask in the use face, formed partly by the portions on the side opposite the substrate, exhibits height variations at sidewalls of the portions that extend perpendicular to the use face. In addition, the mask includes a capping layer that covers at least the sidewalls of the portions.

公开(公告)号：US11270912B2

公开(公告)日：2022-03-08

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US20210183698A1

公开(公告)日：2021-06-17

申请号：US17110631

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Martin O'Toole ,  Christopher Wilson ,  Zsolt Tokei ,  Ryan Ryoung han Kim

IPC: H01L21/768

Abstract: Example embodiments relate to methods for forming via holes self-aligned with metal blocks on substrates. One embodiment includes a method where the substrate includes an interlayer dielectric layer. The method includes forming a metallic layer on the interlayer dielectric layer. The method also includes forming a dielectric layer on the metallic layer and forming a plurality of parallel spacer line structures on the dielectric layer. In addition, the method includes forming a sidewall oxide, a first sacrificial layer, and an opening in the first sacrificial layer. Further, the method includes etching the dielectric layer and removing the first sacrificial layer. Additionally, the method includes forming a second sacrificial layer, forming an opening in the second sacrificial layer, depositing a metal block on the metallic layer, and removing the second sacrificial layer. Still further, the method includes etching the metallic layer and the interlayer dielectric layer to form a via hole.

公开(公告)号：US10592632B2

公开(公告)日：2020-03-17

申请号：US15957409

申请日：2018-04-19

Applicant: IMEC VZW

Inventor： Ryan Ryoung han Kim ,  Jae Uk Lee

IPC: G06F17/00 ,  G06T7/00 ,  G06F17/50 ,  G06N3/08 ,  G03F7/20 ,  G06F3/147

Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.

公开(公告)号：US20200083090A1

公开(公告)日：2020-03-12

申请号：US16563747

申请日：2019-09-06

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Efrain Altamirano Sanchez ,  Ryan Ryoung han Kim

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/763 ,  H01L21/033 ,  H01L29/78

Abstract: A substrate includes on its surface an array of dual stack semiconductor fins, each fin comprising a monocrystalline first portion, a polycrystalline second portion, and a mask third portion. Trenches between the fins are filled with shallow trench isolation (STI) oxide and with polycrystalline material, after which the surface is planarized. Then a second mask is produced on the planarized surface, the second mask defining at least one opening, each defined opening extending across an exposed fin. A thermal oxidation is performed of the polycrystalline material on either side of the exposed fin in each defined opening, thereby producing two oxide strips in each defined opening. Using the second mask and the oxide strips as a mask for self-aligned etching, the material of the exposed dual stack fins is removed and subsequently replaced by an electrically isolating material, thereby creating gate cut structures.

公开(公告)号：US20180307792A1

公开(公告)日：2018-10-25

申请号：US15957409

申请日：2018-04-19

Applicant: IMEC VZW

Inventor： Ryan Ryoung han Kim ,  Jae Uk Lee

IPC: G06F17/50 ,  G06N3/08 ,  G06T7/00

Abstract: Methods and systems for analyzing design of an integrated circuit are described. An example method includes receiving a design layout for an integrated circuit and forming a plurality of images of portions of the design layout. The method also includes, for each image of a portion of the design layout, calculating a Fourier transform representation of the image and extracting values of pre-defined parameters from the Fourier transform representation. The method also includes comparing the extracted parameter values of the plurality of images to create a clustering model by unsupervised machine learning and to sort each image of a portion of the design layout into a cluster defined by the clustering model. The method also includes determining a number of images sorted into at least one cluster defined by the clustering model.

公开(公告)号：US20180261497A1

公开(公告)日：2018-09-13

申请号：US15889043

申请日：2018-02-05

Applicant: IMEC VZW

Inventor： Youssef Drissi ,  Ryan Ryoung han Kim ,  Stephane Lariviere ,  Praveen Raghavan ,  Darko Trivkovic

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/033

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/76843 ,  H01L23/5226

Abstract: A method of forming conductive paths and vias is disclosed. In one aspect, patterns of a hard mask layer are transferred into a dielectric layer by etching to form trenches. The trenches define locations for conductive paths of an upper metallization level. At least one trench is interrupted in a longitudinal direction by a block portion of the hard mask layer, the block portion defining the tip-to-tip location of a pair of the conductive paths to be formed. The trenches extend partially through the dielectric layer in regions exposed by the hard mask layer, thereby deepening first and the second holes to extend completely through the dielectric layer. After removing the hard mask layer, the deepened first and second holes and the trenches are filled with a conductive material to form the conductive paths in the trenches and to form the vias in the deepened first and second holes.