Invention Grant
- Patent Title: Row decoding architecture for a phase-change non-volatile memory device and corresponding row decoding method
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Application No.: US16222484Application Date: 2018-12-17
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Publication No.: US10593400B2Publication Date: 2020-03-17
- Inventor: Antonino Conte
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Slater Matsil, LLP
- Priority: IT102018000000555 20180104
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C8/08

Abstract:
In an embodiment, a non-volatile memory device includes a memory array divided into a plurality of tiles, and a row decoder that includes main row decoding units associated to a respective group of tiles. The row decoded further includes local row decoding units, each associated to a respective tile for carrying out selection and biasing of corresponding word lines based on decoded address signals and biasing signals. Each local row decoding unit has logic-combination modules coupled to a set of word lines and include, for each word line, a pull-down stage for selecting a word line, and a pull-up stage. The pull-up stage is dynamically biased, alternatively, in a strong-biasing condition towards a tile-supply voltage when the word line is not selected, or in a weak-biasing condition when the word line is selected.
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