Invention Grant
- Patent Title: Thrumold post package with reverse build up hybrid additive structure
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Application No.: US16123158Application Date: 2018-09-06
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Publication No.: US10593568B2Publication Date: 2020-03-17
- Inventor: Chan H. Yoo , John F. Kaeding , Ashok Pachamuthu , Mark E. Tuttle
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/31

Abstract:
Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.
Public/Granted literature
- US20190067038A1 THRUMOLD POST PACKAGE WITH REVERSE BUILD UP HYBRID ADDITIVE STRUCTURE Public/Granted day:2019-02-28
Information query
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