公开(公告)号：US20250118722A1

公开(公告)日：2025-04-10

申请号：US18982102

申请日：2024-12-16

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/00

Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.

公开(公告)号：US12218119B2

公开(公告)日：2025-02-04

申请号：US17931284

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/16

Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

公开(公告)号：US12211814B2

公开(公告)日：2025-01-28

申请号：US18212665

申请日：2023-06-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US20240070069A1

公开(公告)日：2024-02-29

申请号：US18215474

申请日：2023-06-28

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11824010B2

公开(公告)日：2023-11-21

申请号：US17682734

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Owen Fay ,  Chan H. Yoo

IPC: H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/823475 ,  H01L23/147 ,  H01L23/5383 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L25/18 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/2518 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1443

Abstract: Described are semiconductor interposer, and microelectronic device assemblies incorporating such semiconductor interposers. The described interposers include multiple redistribution structures on each side of the core; each of which may include multiple individual redistribution layers. The interposers may optionally include circuit elements, such as passive and/or active circuit. The circuit elements may be formed at least partially within the semiconductor core.

公开(公告)号：US11728307B2

公开(公告)日：2023-08-15

申请号：US17236499

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/3512

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US11581231B2

公开(公告)日：2023-02-14

申请号：US16447835

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/66 ,  H01L23/18 ,  H01L23/373 ,  H01L23/16

Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

公开(公告)号：US11416437B2

公开(公告)日：2022-08-16

申请号：US16720976

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G11C7/10 ,  G06F11/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

公开(公告)号：US11309285B2

公开(公告)日：2022-04-19

申请号：US16440328

申请日：2019-06-13

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Chan H. Yoo ,  Mark E. Tuttle

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/532 ,  H01L23/00

Abstract: Semiconductor device packages and associated assemblies are disclosed herein. In some embodiments, the semiconductor device package includes a substrate having a first side and a second side opposite the first side, a first metallization layer positioned at the first side of the substrate, and a second metallization layer in the substrate and electrically coupled to the first metallization layer. The semiconductor device package further includes a metal bump electrically coupled to the first metallization layer and a divot formed at the second side of the substrate and aligned with the metal bump. The divot exposes a portion of the second metallization layer and enables the portion to electrically couple to another semiconductor device package.

公开(公告)号：US20210407882A1

公开(公告)日：2021-12-30

申请号：US17061435

申请日：2020-10-01

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Xiaopeng Qu ,  Chan H. Yoo

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L23/367

Abstract: Semiconductor device assemblies are provided with a package substrate including one or more layers of thermally conductive material configured to conduct heat generated by one or more of semiconductor dies of the assemblies laterally outward towards an outer edge of the assembly. The layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. The layer of thermally conductive material can be provided via deposition (e.g., sputtering, PVD, CVD, or ALD), via adhering a film comprising the layer of thermally conductive material to an outer surface of the package substrate, or via embedding a film comprising the layer of thermally conductive material to within the package substrate.