Invention Grant
- Patent Title: Molded die last chip combination
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Application No.: US15961222Application Date: 2018-04-24
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Publication No.: US10593628B2Publication Date: 2020-03-17
- Inventor: Milind S. Bhagavat , Rahul Agarwal
- Applicant: Milind S. Bhagavat , Rahul Agarwal
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agent Timothy M. Honeycutt
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L23/538 ; H01L25/00 ; H01L21/48 ; H01L21/56 ; H01L25/18 ; H01L23/522 ; H01L23/31 ; H01L23/00 ; H01L23/52

Abstract:
Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.
Public/Granted literature
- US20190326221A1 MOLDED DIE LAST CHIP COMBINATION Public/Granted day:2019-10-24
Information query
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