公开(公告)号：US10593628B2

公开(公告)日：2020-03-17

申请号：US15961222

申请日：2018-04-24

申请人： Milind S. Bhagavat ,  Rahul Agarwal

发明人： Milind S. Bhagavat ,  Rahul Agarwal

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/18 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00 ,  H01L23/52

摘要： Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US10727204B2

公开(公告)日：2020-07-28

申请号：US15991573

申请日：2018-05-29

申请人： Rahul Agarwal ,  Milind S. Bhagavat

发明人： Rahul Agarwal ,  Milind S. Bhagavat

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

摘要： Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

公开(公告)号：US10593620B2

公开(公告)日：2020-03-17

申请号：US15965576

申请日：2018-04-27

申请人： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

发明人： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

摘要： Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.

公开(公告)号：US10529693B2

公开(公告)日：2020-01-07

申请号：US15826054

申请日：2017-11-29

申请人： Rahul Agarwal ,  Milind S. Bhagavat

发明人： Rahul Agarwal ,  Milind S. Bhagavat

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

摘要： Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a front side and a back side and plural through chip vias. The through chip vias have a first footprint. The back side is configured to have a second semiconductor chip stacked thereon. The second semiconductor chip includes plural interconnects that have a second footprint larger than the first footprint. The back side includes a backside interconnect structure configured to connect to the interconnects and provide fanned-in pathways to the through chip vias.

公开(公告)号：US10510721B2

公开(公告)日：2019-12-17

申请号：US15675214

申请日：2017-08-11

申请人： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

发明人： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

IPC分类号： H01L25/065 ,  H01L23/29 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/36

摘要： Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

公开(公告)号：US20190326273A1

公开(公告)日：2019-10-24

申请号：US15961123

申请日：2018-04-24

申请人： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

发明人： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC分类号： H01L25/18 ,  H01L23/433 ,  H01L23/538 ,  H01L23/498 ,  H01L25/00

摘要： Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20190051633A1

公开(公告)日：2019-02-14

申请号：US15675214

申请日：2017-08-11

申请人： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

发明人： Milind S. Bhagavat ,  Lei Fu ,  Ivor Barber ,  Chia-Ken Leong ,  Rahul Agarwal

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/29 ,  H01L23/528

摘要： Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

公开(公告)号：US10714462B2

公开(公告)日：2020-07-14

申请号：US15961123

申请日：2018-04-24

申请人： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

发明人： Milind S. Bhagavat ,  Rahul Agarwal ,  Gabriel H. Loh

IPC分类号： H01L25/00 ,  H01L25/18 ,  H01L23/538 ,  H01L23/498 ,  H01L23/433 ,  H01L23/00

摘要： Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.

公开(公告)号：US20190371763A1

公开(公告)日：2019-12-05

申请号：US15991573

申请日：2018-05-29

申请人： Rahul Agarwal ,  Milind S. Bhagavat

发明人： Rahul Agarwal ,  Milind S. Bhagavat

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

摘要： Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

公开(公告)号：US20190326257A1

公开(公告)日：2019-10-24

申请号：US15960937

申请日：2018-04-24

申请人： Rahul Agarwal ,  Milind S. Bhagavat ,  Lei Fu

发明人： Rahul Agarwal ,  Milind S. Bhagavat ,  Lei Fu

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

摘要： Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer structure that has plural conductor structures and plural glass interlevel dielectric layers. A glass encapsulant layer is positioned on the redistribution layer structure. A first semiconductor chip and a second semiconductor chip are positioned in the glass encapsulant layer and electrically connected by at least some of the conductor structures. A cap layer is on the encapsulant layer.