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    Double side wafer grinder and methods for assessing workpiece nanotopology
    4.
    发明授权
    Double side wafer grinder and methods for assessing workpiece nanotopology 有权
    双面晶圆研磨机和评估工件纳米拓扑学的方法

    公开(公告)号：US07601049B2

    公开(公告)日：2009-10-13

    申请号：US11617433

    申请日：2006-12-28

    申请人： Sumeet S. Bhagavat ,  Milind S. Bhagavat ,  Roland R. Vandamme ,  Tomomi Komura

    发明人： Sumeet S. Bhagavat ,  Milind S. Bhagavat ,  Roland R. Vandamme ,  Tomomi Komura

    IPC分类号： B24B49/00

    CPC分类号： B24B37/28 ,  B24B7/228 ,  B24B49/02

    摘要： A double side grinder comprises a pair of grinding wheels and a pair of hydrostatic pads operable to hold a flat workpiece (e.g., semiconductor wafer) so that part of the workpiece is positioned between the grinding wheels and part of the workpiece is positioned between the hydrostatic pads. At least one sensor measures a distance between the workpiece and the respective sensor for assessing nanotopology of the workpiece. In a method of the invention, a distance to the workpiece is measured during grinding and used to assess nanotopology of the workpiece. For instance, a finite element structural analysis of the workpiece can be performed using sensor data to derive at least one boundary condition. The nanotopology assessment can begin before the workpiece is removed from the grinder, providing rapid nanotopology feedback. A spatial filter can be used to predict the likely nanotopology of the workpiece after further processing.

    摘要翻译： 双面研磨机包括一对砂轮和一对静压垫，其可操作以保持平坦工件（例如，半导体晶片），使得工件的一部分位于砂轮之间并且部分工件位于静水压 垫 至少一个传感器测量工件和相应传感器之间的距离，用于评估工件的纳米拓扑学。 在本发明的方法中，在研磨期间测量与工件的距离，并用于评估工件的纳米拓扑学。 例如，可以使用传感器数据来执行工件的有限元结构分析以导出至少一个边界条件。 纳米技术评估可以在从研磨机上取出工件之前开始，提供快速的纳米拓扑反馈。 可以使用空间滤波器来进一步处理后预测工件的可能纳米拓扑。

    Die stacking for multi-tier 3D integration
    5.
    发明授权
    Die stacking for multi-tier 3D integration 有权

    公开(公告)号：US10727204B2

    公开(公告)日：2020-07-28

    申请号：US15991573

    申请日：2018-05-29

    申请人： Rahul Agarwal ,  Milind S. Bhagavat

    发明人： Rahul Agarwal ,  Milind S. Bhagavat

    IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78

    摘要： Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

    Fan-out package with multi-layer redistribution layer structure
    6.
    发明授权
    Fan-out package with multi-layer redistribution layer structure 有权

    公开(公告)号：US10593620B2

    公开(公告)日：2020-03-17

    申请号：US15965576

    申请日：2018-04-27

    申请人： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

    发明人： Rahul Agarwal ,  Milind S. Bhagavat ,  Priyal Shah

    IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

    摘要： Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer (RDL) structure. The RDL structure includes plural metallization layers and plural polymer layers. One of the polymer layers is positioned over one of the metallization layers. The one of the metallization layers has conductor traces. The one of the polymer layers has an upper surface that is substantially planar at least where the conductor traces are positioned. A semiconductor chip is positioned on and electrically connected to the RDL structure. A molding layer is positioned on the RDL structure and at least partially encases the semiconductor chip.

    Methods of Grinding Semiconductor Wafers Having Improved Nanotopology
    8.
    发明申请
    Methods of Grinding Semiconductor Wafers Having Improved Nanotopology 有权
    研究具有改进的纳米学的半导体晶片的方法

    公开(公告)号：US20110101504A1

    公开(公告)日：2011-05-05

    申请号：US12899262

    申请日：2010-10-06

    申请人： Milind S. Bhagavat ,  Puneet Gupta ,  Roland R. Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

    发明人： Milind S. Bhagavat ,  Puneet Gupta ,  Roland R. Vandamme ,  Takuto Kazama ,  Noriyuki Tachi

    IPC分类号： H01L29/30 ,  B24B1/00

    CPC分类号： B24B7/228 ,  B24B7/17 ,  B24B37/08 ,  B24B37/28 ,  B24B41/061

    摘要： Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

    摘要翻译： 本文公开了用静压垫保持工件的方法。 衬垫包括形成在与晶片直接相对的身体的表面中的静水压凹坑。 凹穴适于接收流体通过主体并进入凹穴，以在主体面和工件之间提供阻挡物，同时在研磨期间仍然施加压力以保持工件。 静压垫允许晶片相对于垫围绕其公共轴线旋转。 当砂轮相对于静液压垫移动或倾斜时，袋被定向成减小在晶片中产生的流体静力弯矩，有助于防止通常由砂轮的移动和倾斜引起的晶片表面的纳米拓扑降解。

    INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR
    9.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED VOLTAGE REGULATOR 审中-公开

    公开(公告)号：US20200312766A1

    公开(公告)日：2020-10-01

    申请号：US16367731

    申请日：2019-03-28

    申请人： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

    发明人： Milind S. Bhagavat ,  Rahul Agarwal ,  Chia-Hao Cheng

    IPC分类号： H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

    摘要： Various semiconductor chip devices and methods of making the same are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer (RDL) structure having a first plurality of conductor traces, a first molding layer on the first RDL structure, plural conductive pillars in the first molding layer, each of the conductive pillars including a first end and a second end, a second RDL structure on the first molding layer, the second RDL structure having a second plurality of conductor traces, and wherein some of the conductive pillars are electrically connected between some of the first plurality of conductor traces and some of the second plurality of conductor traces to provide a first inductor coil.