- Patent Title: Methods of interconnect for high density 2.5D and 3D integration
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Application No.: US15473294Application Date: 2017-03-29
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Publication No.: US10593638B2Publication Date: 2020-03-17
- Inventor: Jaspreet Singh Gandhi , Suresh Ramalingam , Henley Liu
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L23/498

Abstract:
Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.
Public/Granted literature
- US20180286826A1 METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION Public/Granted day:2018-10-04
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