公开(公告)号：US10971474B1

公开(公告)日：2021-04-06

申请号：US16289975

申请日：2019-03-01

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.

公开(公告)号：US20180358280A1

公开(公告)日：2018-12-13

申请号：US15617774

申请日：2017-06-08

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Henley Liu ,  Tien-Yu Lee ,  Gamal Refai-Ahmed ,  Myongseob Kim ,  Ferdinand F. Fernandez ,  Ivor G. Barber ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/10 ,  H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a lid with recessed areas in the inner surfaces of the lid. The recessed areas (e.g., trenches) provide receptacles for accepting a portion of a thermal interface material (TIM) that may be forced out when the lid is positioned on the TIM above one or more integrated circuit (IC) dies during fabrication of the IC package. In this manner, the TIM bond line thickness (BLT) between the lid and the IC die(s) may be reduced for decreased thermal resistance, but sufficient interfacial adhesion is provided for the IC package with such a lid to avoid TIM delamination.

公开(公告)号：US08810269B2

公开(公告)日：2014-08-19

申请号：US13630215

申请日：2012-09-28

Applicant: Xilinx, Inc.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: G01R31/3187

CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。

公开(公告)号：US12068257B1

公开(公告)日：2024-08-20

申请号：US17136721

申请日：2020-12-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Yun Wu ,  Cheang Whang Chang

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/528

Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

公开(公告)号：US11355412B2

公开(公告)日：2022-06-07

申请号：US16147286

申请日：2018-09-28

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Gamal Refai-Ahmed ,  Henley Liu ,  Myongseob Kim ,  Tien-Yu Lee ,  Suresh Ramalingam ,  Cheang-Whang Chang

IPC: H01L23/367 ,  H01L23/427 ,  H01L25/18 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065 ,  H01L25/07

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

公开(公告)号：US20200006186A1

公开(公告)日：2020-01-02

申请号：US16024670

申请日：2018-06-29

Applicant: Xilinx, Inc.

Inventor： Hong-Tsz Pan ,  Jonathan Chang ,  Nui Chong ,  Henley Liu ,  Gamal Refai-Ahmed ,  Suresh Ramalingam

IPC: H01L23/367 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/528

Abstract: A method and apparatus are provided that includes an integrated circuit die having an in-chip heat sink, along with an electronic device and a chip package having the same, and methods for fabricating the same. In one example, an integrated circuit die has an in-chip heat sink that separates a high heat generating integrated circuit from another integrated circuit disposed within the die. The in-chip heat sink provides a highly conductive heat transfer path from interior portions of the die to at least one exposed die surface.

公开(公告)号：US11901338B2

公开(公告)日：2024-02-13

申请号：US17515354

申请日：2021-10-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

IPC: G01R31/28 ,  H01L21/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2225/06596

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

公开(公告)号：US20180286826A1

公开(公告)日：2018-10-04

申请号：US15473294

申请日：2017-03-29

Applicant: Xilinx, Inc.

Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US20140091819A1

公开(公告)日：2014-04-03

申请号：US13630215

申请日：2012-09-28

Applicant: XILINX, INC.

Inventor： Yuqing Gong ,  Henley Liu ,  Myongseob Kim ,  Suresh P. Parameswaran ,  Cheang-Whang Chang ,  Boon Y. Ang

IPC: G01R31/3187

CPC classification number: G01R31/31926 ,  G01R31/2812 ,  G01R31/31717 ,  G01R31/31723 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: An integrated circuit (IC) comprises routing circuitry including a plurality of signal line segments in routing layers of the IC, and a plurality of micro-bump contacts coupled to the routing circuitry. The IC includes a plurality of test circuits coupled to respective subsets of the plurality of signal line segments. Each test circuit is configured to connect micro-bump contacts in the respective subset to form first and second sets of daisy chains. Each test circuit is configured to test the first and second sets of daisy chains for open circuits and test for short circuits between the first and second sets of daisy chains. Each test circuit is configured to determine the locations of detected open circuits and determine the locations of detected short circuits.

Abstract translation: 集成电路（IC）包括路由电路，其包括在IC的路由层中的多个信号线段以及耦合到路由电路的多个微突点接触。 IC包括耦合到多个信号线段的相应子集的多个测试电路。 每个测试电路被配置为连接相应子集中的微凸块触点以形成第一组和第二组菊花链。 每个测试电路被配置为测试用于开路的第一和第二组菊花链，并测试第一组和第二组菊花链之间的短路。 每个测试电路被配置为确定检测到的开路的位置并确定检测到的短路的位置。