Invention Grant
- Patent Title: Double-gate MOS transistor with increased breakdown voltage
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Application No.: US16036240Application Date: 2018-07-16
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Publication No.: US10593772B2Publication Date: 2020-03-17
- Inventor: Christian Rivero , Julien Delalleau
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Agency: Crowe & Dunlevy
- Priority: FR1756935 20170721
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L27/11521 ; H01L29/788 ; H01L29/78 ; H01L21/28 ; H01L29/66 ; H01L27/11524

Abstract:
A MOS transistor located in and on a semiconductor substrate has a drain region, a source region and a conductive gate region. The conductive gate region includes a first conductive gate region that is insulated from the semiconductor substrate and a second conductive gate region that is insulated from and located above the first conductive gate region. A length of the first conductive gate region, measured in the drain-source direction, is greater than a length of the second conductive gate region, also measured in the drain-source direction. The first conductive gate region protrudes longitudinally in the drain-source direction beyond the second conductive gate region at least on one side of the second conductive gate region so as to extend over at least one of the source and drain regions.
Public/Granted literature
- US20190027566A1 DOUBLE-GATE MOS TRANSISTOR WITH INCREASED BREAKDOWN VOLTAGE Public/Granted day:2019-01-24
Information query
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