Invention Grant
- Patent Title: Mitigation of simultaneous switching output effects
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Application No.: US15785547Application Date: 2017-10-17
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Publication No.: US10594314B2Publication Date: 2020-03-17
- Inventor: Nitin Kumar Chhabra , Hemant Kalidas Wadhavankar , Abhijit Anilkumar Jawkar
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee: SEAGATE TECHNOLOGY LLC
- Current Assignee Address: US CA Cupertino
- Agency: Westman, Champlin & Koehler, P.A.
- Main IPC: H03K17/16
- IPC: H03K17/16 ; H03K17/00 ; G01R31/317 ; H03K17/28 ; G11C29/00 ; G06F13/40

Abstract:
Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.
Public/Granted literature
- US20190115912A1 MITIGATION OF SIMULTANEOUS SWITCHING OUTPUT EFFECTS Public/Granted day:2019-04-18
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