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公开(公告)号：US10585996B2
公开(公告)日：2020-03-10
申请号：US15869542
申请日：2018-01-12
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Nitin Kumar Chhabra
IPC: G06F17/50 , G01R21/133
Abstract: Systems and methods for die resistance-capacitance (RC) extraction and validation are described. In one embodiment, the method includes generating a chip power model (CPM) based at least in part on single domain excitation to determine a die capacitance; and performing loop-based static IR drop analysis to determine a die resistance for each power domain of a die. In some cases, the generating of the chip power model (CPM) includes generating a separate CPM for each power domain of the die.
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公开(公告)号：US10594314B2
公开(公告)日：2020-03-17
申请号：US15785547
申请日：2017-10-17
Applicant: Seagate Technology LLC
Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.
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公开(公告)号：US20190267069A1
公开(公告)日：2019-08-29
申请号：US15906998
申请日：2018-02-27
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra
IPC: G11C11/409 , G11C11/408 , G11C11/4076
Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
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公开(公告)号：US10541020B2
公开(公告)日：2020-01-21
申请号：US15906998
申请日：2018-02-27
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra
IPC: G11C7/00 , G11C11/409 , G11C11/4076 , G11C11/408 , G11C7/10 , G06F13/42 , G11C11/4096 , G11C7/22
Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
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公开(公告)号：US20190115912A1
公开(公告)日：2019-04-18
申请号：US15785547
申请日：2017-10-17
Applicant: Seagate Technology LLC
IPC: H03K17/16 , H03K17/00 , H03K17/28 , G01R31/317
Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.
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Patent Agency Ranking
公开(公告)号：US20180373302A1
公开(公告)日：2018-12-27
申请号：US15633026
申请日：2017-06-26
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra , Pritesh Mahadev Pawaskar
IPC: G06F1/32
Abstract: The disclosed technology provides methods for performing a power delivery network analysis of the memory unit I/O power domain. The methods include performing a signal and power integrity analysis for a memory unit I/O power domain to extract characteristics of a current waveform, determining characteristics of an expected waveform based on a current response for the memory unit I/O power domain, and determining whether the characteristics of the current waveform and the characteristics of the expected waveform are within a tolerance limit. The method also includes various remedial operations and CPM regeneration which may iteratively occur until the waveform matches and final CPM is generated which is use for PDN analysis.
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公开(公告)号：US20200152254A1
公开(公告)日：2020-05-14
申请号：US16746365
申请日：2020-01-17
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra
IPC: G11C11/409 , G11C7/22 , G11C11/4096 , G06F13/42 , G11C7/10 , G11C11/408 , G11C11/4076
Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
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公开(公告)号：US10585999B2
公开(公告)日：2020-03-10
申请号：US15869484
申请日：2018-01-12
Applicant: SEAGATE TECHNOLOGY LLC
Inventor： Nitin Kumar Chhabra , Rohit Halba
IPC: G06F17/50
Abstract: Systems and methods for selecting die and package parasitic for an input-output (IO) power domain are described. In one embodiment, the method includes determining a minimum on-die decoupling capacitance based at least in part on a product of a number of simultaneously switching IOs of the die and a maximum instantaneous current of an IO; determining a maximum package inductance based at least in part on a maximum operating frequency of an IC and a target impedance of a power delivery network of the die, the IC package, and a printed circuit board (PCB); and determining a maximum die resistance based at least in part on preventing the maximum die resistance from exceeding a maximum static IR drop of the die.
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公开(公告)号：US10560116B2
公开(公告)日：2020-02-11
申请号：US15854222
申请日：2017-12-26
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra , Rohit Halba , Shashi Kumar Shaw , Shrikrishna Nana Mehetre
IPC: H03M11/00 , H03M7/30 , H04L25/02 , G06F13/42 , H04L27/06 , H03M5/16 , H03K19/0185 , H04L25/49 , H03K19/0175
Abstract: A method includes, for an N-bit system on chip (SoC), calculating a minimum number of bits NP that can simultaneously switch without producing an error across a complete warranty time period of the N-bit SoC. The method also includes carrying out power estimation calculations for the N-bit SoC using the calculated minimum number of bits NP.
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公开(公告)号：US10896721B2
公开(公告)日：2021-01-19
申请号：US16746365
申请日：2020-01-17
Applicant: Seagate Technology LLC
Inventor： Nitin Kumar Chhabra
IPC: G11C7/00 , G11C11/409 , G11C11/4076 , G11C11/408 , G11C7/10 , G06F13/42 , G11C11/4096 , G11C7/22
Abstract: The disclosed controller includes a DDR architecture that includes a dual-channel interface designed to include DQS IO ports configured to generate a first DQS signal that is a distance of substantially 0.125 times the period of a clock signal (ΔT denoting the 0.125 of the period of the clock signal) ahead of a rising edge of the clock signal and a second DQS signal that is a distance of substantially 0.125 times the period of the clock signal behind the rising edge of a clock signal. If ΔT is more than a tDQSS then ΔT is set to tDQSS, where tDQSS is a maximum allowable time between either DQS signal and the rising edge of the clock signal.
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