公开(公告)号：US20190115912A1

公开(公告)日：2019-04-18

申请号：US15785547

申请日：2017-10-17

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Hemant Kalidas Wadhavankar ,  Abhijit Anilkumar Jawkar

IPC: H03K17/16 ,  H03K17/00 ,  H03K17/28 ,  G01R31/317

Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.

公开(公告)号：US10594314B2

公开(公告)日：2020-03-17

申请号：US15785547

申请日：2017-10-17

Applicant: Seagate Technology LLC

Inventor： Nitin Kumar Chhabra ,  Hemant Kalidas Wadhavankar ,  Abhijit Anilkumar Jawkar

IPC: H03K17/16 ,  H03K17/00 ,  G01R31/317 ,  H03K17/28 ,  G11C29/00 ,  G06F13/40

Abstract: Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.