- 专利标题: Logic-driven layout verification
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申请号: US13017788申请日: 2011-01-31
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公开(公告)号: US10596219B2公开(公告)日: 2020-03-24
- 发明人: Sridhar Srinivasan , Fedor G. Pikus , Patrick D. Gibson , Padmaja Susarla
- 申请人: Sridhar Srinivasan , Fedor G. Pikus , Patrick D. Gibson , Padmaja Susarla
- 申请人地址: US OR Wilsonville
- 专利权人: Mentor Graphics Corporation
- 当前专利权人: Mentor Graphics Corporation
- 当前专利权人地址: US OR Wilsonville
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; A61K38/00 ; A61K39/395 ; A61K47/02 ; A61K38/48
摘要:
A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.
公开/授权文献
- US20110320990A1 LOGIC-DRIVEN LAYOUT VERIFICATION 公开/授权日:2011-12-29
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