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公开(公告)号：US20100223583A1
公开(公告)日：2010-09-02
申请号：US12777226
申请日：2010-05-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US20100185995A1
公开(公告)日：2010-07-22
申请号：US12541906
申请日：2009-08-14
申请人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
发明人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
摘要翻译： 用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。 使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。 基于互连线的特性和指定的最大阻抗分量值创建分析窗口。 窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。 一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。 如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。
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公开(公告)号：US20190146847A1
公开(公告)日：2019-05-16
申请号：US15873827
申请日：2018-01-17
申请人： Patrick D. Gibson , Robert A. Todd
发明人： Patrick D. Gibson , Robert A. Todd
IPC分类号： G06F9/50
摘要： Methods and apparatus for dynamic distributed resource management as can be used in large-scale electronic design automation processes, are disclosed. In some examples of the disclosed technology, a method for dynamic remote resource allocation includes receiving a request for one or more remote resources, identifying one or more resources available to satisfy the request, initiating one or more separate processes for the respective available resources, preparing the respective resources for use as remote resources, by the one or more separate processes running in parallel, and as a given resource of the one or more available resources completes the preparation, allocating the given resource as a remote resource. In some examples, allocated resources are dynamically integrated into the processing of the job. In some examples, as a given resource of the one or more available resources is allocated, tasking the given resource with a portion of the job.
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公开(公告)号：US08510690B2
公开(公告)日：2013-08-13
申请号：US12777226
申请日：2010-05-10
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
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公开(公告)号：US20130080985A1
公开(公告)日：2013-03-28
申请号：US13426595
申请日：2012-03-21
申请人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
发明人： Fedor G. Pikus , Ziyang Lu , Patrick D. Gibson
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified. If there are any remaining interconnect lines that have not been determined to exceed the specified maximum impedance component value through the use of the analysis window, then the impedance component values of these remaining interconnect lines can be specifically determined using a parasitic extraction process.
摘要翻译： 用于有效地确定互连线是否具有低于最大规定值的阻抗分量值的技术。 使用指定的最大阻抗分量值来限制通过寄生提取分析过程分析的互连线的数量。 基于互连线的特性和指定的最大阻抗分量值创建分析窗口。 窗口的大小对应于具有指定的最大阻抗分量值的互连线的最小长度。 一旦创建了分析窗口，就检查互连线以确定它们中的任何一个是否到达（或超出）分析窗口，从而可以识别出超过规定的最大阻抗分量值的互连线。 如果通过使用分析窗口还没有确定剩余的互连线未被确定为超过规定的最大阻抗分量值，那么这些剩余互连线的阻抗分量值可以使用寄生提取处理来具体确定。
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公开(公告)号：US07412675B2
公开(公告)日：2008-08-12
申请号：US11202935
申请日：2005-08-12
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US06931613B2
公开(公告)日：2005-08-16
申请号：US10180956
申请日：2002-06-24
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US07716614B2
公开(公告)日：2010-05-11
申请号：US12177018
申请日：2008-07-21
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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公开(公告)号：US10596219B2
公开(公告)日：2020-03-24
申请号：US13017788
申请日：2011-01-31
IPC分类号： G06F17/50 , A61K38/00 , A61K39/395 , A61K47/02 , A61K38/48
摘要： A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.
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公开(公告)号：US20090007039A1
公开(公告)日：2009-01-01
申请号：US12177018
申请日：2008-07-21
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.
摘要翻译： 计算集成电路布局中的电路元件的电学相互作用的方法，而不使整个描述布局的数据库变平坦。 在一个实施例中，分析分层数据库，并且在重复模式的每个实例处重新使用针对重复模式元素进行的电阻和电容计算，并根据局部条件进行调整。 在另一个实施例中，将电路布局转换成多个瓦片，其中对瓦片的中心的电路元件和瓦片的边界区域进行的电阻和电容计算分别计算并组合。 影响不同级别层次的电路元件之间的电气相互作用的环境信息是在较低级别的层次上进行计算，因此不需要对重复单元格的每个放置进行此类计算，因此不需要促进所有相互作用的元素 到相同的层次级别来计算电相互作用。
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