Invention Grant
- Patent Title: Parallel memory self-testing
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Application No.: US15891789Application Date: 2018-02-08
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Publication No.: US10600495B2Publication Date: 2020-03-24
- Inventor: Devanathan Varadarajan , Sumant Kale
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Ebby Abraham; Charles A. Brill; Frank D. Cimino
- Main IPC: G11C29/38
- IPC: G11C29/38 ; G11C29/26 ; G11C29/36

Abstract:
In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.
Public/Granted literature
- US20180374556A1 PARALLEL MEMORY SELF-TESTING Public/Granted day:2018-12-27
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