Invention Grant
- Patent Title: Ultrathin layer for forming a capacitive interface between joined integrated circuit component
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Application No.: US16020654Application Date: 2018-06-27
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Publication No.: US10600760B2Publication Date: 2020-03-24
- Inventor: Belgacem Haba , Arkalgud R. Sitaram
- Applicant: Invensas Corporation
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/64 ; H01L23/48 ; H01L21/02 ; H01L21/311 ; H01L25/00 ; H01L23/00

Abstract:
Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.
Public/Granted literature
- US20180366446A1 Ultrathin Layer for Forming a Capacitive Interface Between Joined Integrated Circuit Component Public/Granted day:2018-12-20
Information query
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