Invention Grant
- Patent Title: Coherent interconnect power reduction using hardware controlled split snoop directories
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Application No.: US15259697Application Date: 2016-09-08
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Publication No.: US10606339B2Publication Date: 2020-03-31
- Inventor: Christophe Avoinne , Luc Montperrus , Philippe Boucard , Rakesh Kumar Gupta
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: The Marbury Law Group/Qualcomm
- Main IPC: G06F1/3296
- IPC: G06F1/3296 ; G06F12/0831 ; G06F1/3287 ; G06F1/3206 ; G06F1/3234 ; G06F9/54

Abstract:
Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.
Public/Granted literature
- US20180067542A1 Coherent Interconnect Power Reduction Using Hardware Controlled Split Snoop Directories Public/Granted day:2018-03-08
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