公开(公告)号：US10606339B2

公开(公告)日：2020-03-31

申请号：US15259697

申请日：2016-09-08

Applicant: QUALCOMM Incorporated

Inventor： Christophe Avoinne ,  Luc Montperrus ,  Philippe Boucard ,  Rakesh Kumar Gupta

IPC: G06F1/3296 ,  G06F12/0831 ,  G06F1/3287 ,  G06F1/3206 ,  G06F1/3234 ,  G06F9/54

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

公开(公告)号：US20180067542A1

公开(公告)日：2018-03-08

申请号：US15259697

申请日：2016-09-08

Applicant: QUALCOMM Incorporated

Inventor： Christophe Avoinne ,  Luc Montperrus ,  Philippe Boucard ,  Rakesh Kumar Gupta

IPC: G06F1/32 ,  G06F9/54

CPC classification number: G06F1/3296 ,  G06F1/32 ,  G06F9/54 ,  G06F12/0833 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

公开(公告)号：US11520706B2

公开(公告)日：2022-12-06

申请号：US17244398

申请日：2021-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Alain Artieri ,  Rakesh Kumar Gupta ,  Subbarao Palacharla ,  Kedar Bhole ,  Laurent Rene Moll ,  Carlo Spitale ,  Sparsh Singhai ,  Shyamkumar Thoziyoor ,  Gopi Tummala ,  Christophe Avoinne ,  Samir Ginde ,  Syed Minhaj Hassan ,  Jean-Jacques Lecler ,  Luigi Vinci

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/12

Abstract: Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.