- 专利标题: Frequency-agile clock multiplier
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申请号: US16247894申请日: 2019-01-15
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公开(公告)号: US10608652B2公开(公告)日: 2020-03-31
- 发明人: Jared L. Zerbe , Brian S. Leibowitz , Masum Hossain
- 申请人: Rambus Inc.
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理商 Charles Shemwell
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; H03L7/099 ; H03K5/00 ; H03K5/13 ; H03K3/03 ; H03K5/14 ; H03L7/24 ; H03L7/16
摘要:
In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
公开/授权文献
- US20190222217A1 Frequency-agile clock multiplier 公开/授权日:2019-07-18
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