Systems, apparatuses, and methods for efficiently implementing clock gating circuitry. A multi-bit clock gating cell is placed on the die of an integrated circuit and replaces at least two single-bit clock gating cells that were to be placed on the die. Each single-bit clock gating cell receives a single clock enable signal and generates a single gated clock signal. Each multi-bit clock gating cell receives multiple clock enable signals and generates multiple gated clock signals based on a single common received clock signal. Conditions for determining whether two or more single-bit clock gating cells are replaced by a multi-bit clock gating cell include a distance between two single-bit clock gating cells, a load driven by any one of the two single-bit clock gating cells and an activity level of a common single clock received by at least two single-bit clock gating cells is above a respective threshold.