公开(公告)号：US10162914B1

公开(公告)日：2018-12-25

申请号：US15673467

申请日：2017-08-10

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Suparn Vats

IPC: G01R31/3177 ,  G06F17/50 ,  G06F17/30 ,  H03K19/003 ,  G01R31/3183 ,  G01R31/3185

Abstract: A method and apparatus for forcing equivalent outputs at start-up for replicated sequential circuits is disclosed. An integrated circuit (IC) includes first and second clocked logic circuits each coupled to receive a clock signal common to both, and each configured to produce equivalent logical outputs based on a common set of logic inputs. The IC further includes an equivalence circuit coupled to the outputs of each of the first and second clocked logic circuits. During a system start-up (e.g., power on) and before the clock signal has been applied, the equivalence circuit may detect if the outputs of the to first and second clocked logic circuits originally come up in different states. Responsive to determining that the outputs of the first and second clocked logic circuits are different, the equivalence circuit may cause the outputs to be forced to the same logical state.

公开(公告)号：US09564898B2

公开(公告)日：2017-02-07

申请号：US14622111

申请日：2015-02-13

Applicant: Apple Inc.

Inventor： Shingo Suzuki ,  Harsha Krishnamurthy ,  Edvin Catovic ,  Rajat Goel ,  Manoj Gopalan

IPC: H03K19/003 ,  H03K19/00

CPC classification number: H03K19/00361 ,  H03K19/0013 ,  H03K19/0016

Abstract: In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个电源门控块和功率管理器电路。 功率管理器电路可以被配置为为每个电源门控块和块使能时钟生成块使能。 电源门控块可以在电源门控块中产生各种电源开关段的本地块使能。 特别地，电源门控块可以包括从电源管理器电路接收块使能的一组串联的触发器。 功率门控块可以包括为每个功率开关段提供本地块使能的一组多路复用器（多路复用器）。 多路复用器的一个输入耦合到块使能，另一个输入耦合到通过其它功率开关段之一传播的另一个功能。 因此，可以控制多路复用器来选择传播的使能或输入块使能。

公开(公告)号：US09513658B2

公开(公告)日：2016-12-06

申请号：US14641619

申请日：2015-03-09

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Muthukumaravelu Velayoudame

IPC: G06F1/10 ,  G06F1/14 ,  G06F17/50 ,  H03K19/00

CPC classification number: G06F1/10 ,  G06F1/14 ,  G06F17/5022 ,  G06F17/5031 ,  H03K19/0016

Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Abstract translation: 在集成电路设计方法中使用的过程可以用于评估和组织用于集成电路设计的多位定时存储设备（例如，多位触发器）内的各个位（例如，触发器）。 该过程可以包括基于所评估的定时松弛来评估比特的定时松弛，排序和/或分配比特，以及使用排序和/或分配的比特重新映射多比特定时存储的设备。 重新映射的多位定时存储设备可以应用一个或多个定时校正。 定时校正可以包括有用的时钟偏移或调整重映射的多位定时存储设备的大小（例如，增大或缩小尺寸）。

公开(公告)号：US09454632B1

公开(公告)日：2016-09-27

申请号：US14599177

申请日：2015-01-16

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L27/0207

Abstract: In some embodiments, a method may be directed towards contextual based spare cell assignment for integrated circuits. The method may include reserving a plurality of spare cell areas in which to position spare cells on an integrated circuit. The method may include positioning standard cells as defined by an integrated circuit design for the integrated circuit. In some embodiments, the method may include determining the spare cells to be positioned in the plurality of spare cell areas based upon a population of a plurality of types of cells in a predetermined area. The method may include ensuring that each of the plurality of spare cell areas may include a minimum number of predetermined cells. The method may include positioning a predetermined cell in at least one of the plurality of spare cell areas if the type of predetermined cells is absent in the population of areas adjacent to the predetermined area.

Abstract translation: 在一些实施例中，一种方法可以针对集成电路的基于上下文的备用小区分配。 该方法可以包括保留在集成电路上定位备用单元的多个备用单元区域。 该方法可以包括定位由集成电路的集成电路设计定义的标准单元。 在一些实施例中，该方法可以包括基于预定区域中的多种类型的单元的总体来确定要放置在多个备用单元区域中的备用单元。 该方法可以包括确保多个备用单元区域中的每一个可以包括最小数量的预定单元。 如果在与预定区域相邻的区域的群体中不存在预定小区的类型，则该方法可以包括将预定小区定位在多个备用小区区域中的至少一个中。

公开(公告)号：US20160266604A1

公开(公告)日：2016-09-15

申请号：US14641619

申请日：2015-03-09

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Muthukumaravelu Velayoudame

IPC: G06F1/10 ,  G06F1/14

CPC classification number: G06F1/10 ,  G06F1/14 ,  G06F17/5022 ,  G06F17/5031 ,  H03K19/0016

Abstract: A process utilized in an integrated circuit design methodology may be used to assess and organize individual bits (e.g., flip-flops) within multi-bit clocked storage devices (e.g., multi-bit flip-flops) for use in the integrated circuit design. The process may include assessing timing slacks of the bits, sorting and/or assigning the bits based on the assessed timing slacks, and remapping the multi-bit clocked storage devices using the sorted and/or assigned bits. One or more timing corrections may be applied to the remapped multi-bit clocked storage devices. The timing corrections may include useful clock skewing or resizing (e.g., upsizing or downsizing) of the remapped multi-bit clocked storage devices.

Abstract translation: 在集成电路设计方法中使用的过程可以用于评估和组织用于集成电路设计的多位定时存储设备（例如，多位触发器）内的各个位（例如，触发器）。 该过程可以包括基于所评估的定时松弛来评估比特的定时松弛，排序和/或分配比特，以及使用排序和/或分配的比特重新映射多比特定时存储的设备。 重新映射的多位定时存储设备可以应用一个或多个定时校正。 定时校正可以包括有用的时钟偏移或调整重映射的多位定时存储设备的大小（例如，增大或缩小尺寸）。

公开(公告)号：US11121707B2

公开(公告)日：2021-09-14

申请号：US17112470

申请日：2020-12-04

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy

IPC: H03K5/13 ,  G06F1/08 ,  G06F30/398 ,  H03K5/00 ,  G06F119/12

Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

公开(公告)号：US20210091760A1

公开(公告)日：2021-03-25

申请号：US17112470

申请日：2020-12-04

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy

IPC: H03K5/13 ,  G06F1/08 ,  G06F30/398

Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

公开(公告)号：US10886903B1

公开(公告)日：2021-01-05

申请号：US16545120

申请日：2019-08-20

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy

IPC: H03K5/13 ,  G06F1/08 ,  G06F30/398 ,  H03K5/00 ,  G06F119/12

Abstract: In one embodiment, an integrated circuit may be designed using a library of clocked circuits that have programmable clock delays that may be inserted on the clock input to the clocked circuits. During the design process, timing paths which are challenging due to significant variations across operating states, process corners, and/or temperature may be met by using the clocked circuits with programmable delays and inserting a delay control circuit that programs the delays based on the current operating state, process corner used to manufacture the integrated circuit, and/or temperature. That is, different delays may be selected by the delay control circuit depending on inputs that identify the operating state, the process corner, and/or the temperature. Because the clock delay is intentionally skewed, the timing of the path may be different at different operating states, temperatures, or process corners and thus may meet timing by changing the clock skew during operation.

公开(公告)号：US10650112B1

公开(公告)日：2020-05-12

申请号：US15851134

申请日：2017-12-21

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy

IPC: G06F17/50 ,  H03K3/037 ,  H03K3/012 ,  G06F1/10

Abstract: Systems, apparatuses, and methods for efficiently implementing clock gating circuitry. A multi-bit clock gating cell is placed on the die of an integrated circuit and replaces at least two single-bit clock gating cells that were to be placed on the die. Each single-bit clock gating cell receives a single clock enable signal and generates a single gated clock signal. Each multi-bit clock gating cell receives multiple clock enable signals and generates multiple gated clock signals based on a single common received clock signal. Conditions for determining whether two or more single-bit clock gating cells are replaced by a multi-bit clock gating cell include a distance between two single-bit clock gating cells, a load driven by any one of the two single-bit clock gating cells and an activity level of a common single clock received by at least two single-bit clock gating cells is above a respective threshold.

公开(公告)号：US10296686B1

公开(公告)日：2019-05-21

申请号：US14968022

申请日：2015-12-14

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Ram Subramaniam Gandhi

IPC: G06F17/50

Abstract: Techniques are disclosed relating to reducing dynamic power consumption in integrated circuits. In some embodiments, simulation is performed at one or more stages of a circuit design to identify portions of the circuit with relatively high average clock switching activity, based on an amount of clock gating during the simulation by one or more clock gaters. In some embodiments, sequential circuit elements in the identified portions are specified as candidates for implementation using low-power sequential circuitry. Examples of low-power sequential circuitry include multibit flip flops and flip flops with low clock pin input capacitance. The disclosed techniques may allow automated design tools to significantly reduce dynamic power consumption while still meeting other design parameters such as timing constraints.