Invention Grant
- Patent Title: Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding
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Application No.: US16011139Application Date: 2018-06-18
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Publication No.: US10651153B2Publication Date: 2020-05-12
- Inventor: Richard Fastow , Khaled Hasnat , Prashant Majhi , Owen Jungroth
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law, PC
- Main IPC: H01L27/11548
- IPC: H01L27/11548 ; H01L27/11556 ; H01L25/065 ; G11C16/08 ; H01L23/00 ; G11C16/04 ; H01L27/11573 ; H01L27/06 ; H01L27/11575 ; H01L27/11582 ; H01L25/00 ; G11C5/02

Abstract:
Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.
Public/Granted literature
- US20190043836A1 THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING WAFER-TO-WAFER BONDING Public/Granted day:2019-02-07
Information query
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