公开(公告)号：US10325665B2

公开(公告)日：2019-06-18

申请号：US15836124

申请日：2017-12-08

Applicant: INTEL CORPORATION

Inventor： Richard Fastow ,  Xin Sun ,  Uday Chandrasekhar ,  Krishna K. Parat ,  Camila Jaramillo ,  Purval S. Sule ,  Aliasgar S. Madraswala

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/16 ,  G11C16/34 ,  G11C11/4074 ,  G11C16/04

Abstract: A controller for a NAND memory array is presented. In embodiments, the controller may include circuitry to provide bias voltages to a NAND memory array that includes two or more decks of memory cells, and an output interface coupled to the circuitry and to wordlines (WLs) of the memory array. In embodiments, the circuitry, in a deck erase operation may: apply a first set of bias voltages via the output interface to active WLs of at least a first deck of the two or more decks of memory cells to be erased; and apply a second set of bias voltages via the output interface to active WLs of at least a second deck of the two or more decks of memory cells not to be erased, wherein the first set of bias voltages is lower than the second set of bias voltages.

公开(公告)号：US10651153B2

公开(公告)日：2020-05-12

申请号：US16011139

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen Jungroth

IPC: H01L27/11548 ,  H01L27/11556 ,  H01L25/065 ,  G11C16/08 ,  H01L23/00 ,  G11C16/04 ,  H01L27/11573 ,  H01L27/06 ,  H01L27/11575 ,  H01L27/11582 ,  H01L25/00 ,  G11C5/02

Abstract: Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.

公开(公告)号：US11500446B2

公开(公告)日：2022-11-15

申请号：US16586957

申请日：2019-09-28

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Shankar Natarajan ,  Chang Wan Ha ,  Chee Law ,  Khaled Hasnat ,  Chuan Lin ,  Shafqat Ahmed

IPC: G06F1/32 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G06F1/3234

Abstract: A nonvolatile memory supports a standby state where the memory is ready to receive an access command to execute, and a deep power down state where the memory ignores all access commands. The memory can transition from the standby state to the deep power down state in response to a threshold amount of time in the standby state. Thus, the memory can enter the standby state after a command and then transition to the deep power down state after the threshold time.

公开(公告)号：US10923450B2

公开(公告)日：2021-02-16

申请号：US16437445

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Richard Fastow ,  Khaled Hasnat ,  Prashant Majhi ,  Owen W. Jungroth ,  Krishna Parat

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573 ,  H01L25/18

Abstract: An integrated circuit memory includes a logic circuitry bonded to a memory array. For example, the logic circuitry is formed separately from the memory array, and then the logic circuitry and the memory array are bonded. The logic circuitry facilitates operations of the memory array and includes complementary metal-oxide-semiconductor (CMOS) logic components, such as word line drivers, bit line drivers, sense amplifiers for the memory array. In an example, instead of being bonded to a single memory array, the logic circuitry is bonded to and shared by two memory arrays. For example, the logic circuitry is between two memory arrays. Due to the bonding process, a bonding interface layer is formed. Thus, in such an example, a first bonding interface layer is between the logic circuitry and a first memory array, and a second bonding interface layer is between the logic circuitry and a second memory array.

公开(公告)号：US11322508B2

公开(公告)日：2022-05-03

申请号：US15996116

申请日：2018-06-01

Applicant: Intel Corporation

Inventor： Krishna Parat ,  Richard Fastow

IPC: H01L27/11556 ,  G11C16/04 ,  H01L21/764 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: Flash memory technology is disclosed. In one example, a flash memory component can include a plurality of conductive layers vertically spaced apart from one another and separated by voids, each of the plurality of conductive layers forming a word line. The memory component can also include a vertically oriented conductive channel extending through the plurality of conductive layers. In addition, the flash memory component can include a plurality of memory cells coupling the plurality of conductive layers to the conductive channel. Each word line can be associated with one of the plurality of memory cells. Associated devices, systems, and methods are also disclosed.