Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.