公开(公告)号：US12045188B2

公开(公告)日：2024-07-23

申请号：US16986133

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Daniel Biederman ,  Aniket A Aphale ,  Sharvil Desai ,  Matthew James Webb

IPC: G06F13/40 ,  G06F11/10 ,  H04J3/02

CPC classification number: G06F13/4031 ,  G06F11/1004 ,  H04J3/02

Abstract: Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

公开(公告)号：US10652162B2

公开(公告)日：2020-05-12

申请号：US16024749

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Dan Christian Biederman ,  Matthew James Webb

IPC: H04L12/805 ,  H04L12/721 ,  H04L29/06 ,  H04L29/08

Abstract: Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

公开(公告)号：US12160369B2

公开(公告)日：2024-12-03

申请号：US16276979

申请日：2019-02-15

Applicant: Intel Corporation

Inventor： Chih-Jen Chang ,  Daniel Christian Biederman ,  Matthew James Webb ,  Wing Cheung ,  Jose Niell ,  Robert Hathaway

IPC: H04L47/80 ,  H04L41/042 ,  H04L45/00 ,  H04L47/2425 ,  H04L47/2483 ,  H04L47/62

Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

公开(公告)号：US20190044876A1

公开(公告)日：2019-02-07

申请号：US16024749

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Dan Christian Biederman ,  Matthew James Webb

IPC: H04L12/805 ,  H04L29/06 ,  H04L12/721

Abstract: Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

公开(公告)号：US20190044657A1

公开(公告)日：2019-02-07

申请号：US16145844

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel Christian Biederman ,  Matthew James Webb

IPC: H04L1/00 ,  H04L12/823 ,  H04L29/08 ,  H04L12/851

Abstract: Received undersized Ethernet frames are isolated and discarded in a Media Access Control (MAC) sublayer having a bus width greater than the number of bytes in a received minimum size Ethernet frame. The MAC sublayer maintains one counter to track the total number of undersized frames (undersized frames with good Cyclic Redundancy Check (CRC)) and runts with bad CRC). Undersized Ethernet frames are discarded by the MAC sublayer prior to calculating Cyclic Redundancy Check (CRC) for the Ethernet Frame.

公开(公告)号：US20240394207A1

公开(公告)日：2024-11-28

申请号：US18770975

申请日：2024-07-12

Applicant: Intel Corporation

Inventor： Daniel Biederman ,  Aniket A. Aphale ,  Sharvil Desai ,  Matthew James Webb

IPC: G06F13/40 ,  G06F11/10 ,  H04J3/02

Abstract: Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

公开(公告)号：US11296807B2

公开(公告)日：2022-04-05

申请号：US16452090

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Matthew James Webb ,  Daniel Christian Biederman

IPC: H04W76/12 ,  H04J3/16

Abstract: Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.