Invention Grant
- Patent Title: Metal on both sides with clock gated-power and signal routing underneath
-
Application No.: US16227406Application Date: 2018-12-20
-
Publication No.: US10658291B2Publication Date: 2020-05-19
- Inventor: Donald W. Nelson , Patrick Morrow , Kimin Jun
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/00 ; H01L29/78

Abstract:
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.
Public/Granted literature
- US20190122985A1 METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH Public/Granted day:2019-04-25
Information query
IPC分类: