Gray code counting signal distribution system
Abstract:
A counter distribution system includes an N bit counter to receive a first counting clock to generate a plurality of data bits including lower data bits on lower data bit lines and upper data bits on upper data bit lines. The upper data bits include at least one redundant bit to provide error correction for the counter distribution system. A plurality of latches is coupled to the N bit counter. Each one of the lower data bit lines and each one of the upper data bit lines is coupled to at least one of the latches. The latches are arranged into a plurality of groupings of latches. Each grouping of latches is coupled to a respective latch enable signal. Each latch in each grouping of latches is coupled to latch a respective one of the plurality of data bits in response to the respective latch enable signal.
Information query
Patent Agency Ranking
0/0