Invention Grant
- Patent Title: Memory component with independently enabled data and command interfaces
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Application No.: US16032633Application Date: 2018-07-11
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Publication No.: US10665289B2Publication Date: 2020-05-26
- Inventor: Ian Shaeffer , Lei Luo , Liji Gopalakrishnan
- Applicant: Rambus Inc.
- Applicant Address: US CA Sunnyvale
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA Sunnyvale
- Agent Charles Shemwell
- Main IPC: G11C11/4076
- IPC: G11C11/4076 ; G11C11/4096 ; G11C7/10 ; G11C7/20 ; G11C7/22 ; G11C11/4072 ; G11C11/4074 ; G06F1/3237 ; G06F1/04 ; G06F1/3234 ; G06F1/08 ; G11C11/408

Abstract:
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
Public/Granted literature
- US20190043551A1 MEMORY COMPONENT WITH STAGGERED POWER-DOWN EXIT Public/Granted day:2019-02-07
Information query
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