Memory device with channel discharge before program-verify based on data state and sub-block position
Abstract:
Techniques are disclosed for reducing an injection type of read disturb in a memory device. During a program loop, when NAND strings in a selected sub-block are programmed, a pre-verify voltage pulse is applied to a selected word line and to a select gate transistor to discharge the drain-side channel in NAND strings of unselected sub-blocks. The duration of the pulse can vary for the different unselected sub-blocks and can be based on a sub-block programming order. In another aspect, the duration is higher for initial program loops in a program operation, when lower data states are being verified, and then decreases to a lower level for subsequent program loops when higher data states are being verified.
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