Provided herein is an apparatus that includes an address output circuit configured to output a first address signal including a plurality of bits including a first bit section and a second bit section, and a decoder circuit configured to decode the first address signal to generate a second address signal. The decoder circuit decides an output value of the second address signal based on the first bit section when a value of the second bit section is in a first value range. The decoder circuit decides the output value of the second address signal regardless of the first bit section when a value of the second bit section is in a second value range.