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公开(公告)号：US20170237435A1
公开(公告)日：2017-08-17
申请号：US15485696
申请日：2017-04-12
发明人： Satoshi Yamanaka
IPC分类号： H03K19/0175 , G11C8/10 , G11C8/18 , G11C8/08
CPC分类号： G11C8/08 , G11C5/145 , G11C5/147 , G11C8/10 , G11C8/14 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087 , H03K19/017509 , H03K19/018557
摘要： Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
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公开(公告)号：US10607689B2
公开(公告)日：2020-03-31
申请号：US16416059
申请日：2019-05-17
发明人： Satoshi Yamanaka , Tetsuaki Okahiro
IPC分类号： G11C11/40 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C8/14 , G11C5/02 , G11C8/08 , G11C8/12
摘要： Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.
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公开(公告)号：US11176977B2
公开(公告)日：2021-11-16
申请号：US17183604
申请日：2021-02-24
IPC分类号： G11C8/08 , G11C29/02 , G11C11/408 , G11C29/12
摘要： Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
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公开(公告)号：US20190237128A1
公开(公告)日：2019-08-01
申请号：US15881200
申请日：2018-01-26
发明人： Satoshi Yamanaka , Tetsuaki Okahiro
IPC分类号： G11C11/4091 , G11C11/4074
CPC分类号： G11C11/4091 , G11C11/4074
摘要： Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.
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公开(公告)号：US20210398585A1
公开(公告)日：2021-12-23
申请号：US16904004
申请日：2020-06-17
IPC分类号： G11C11/408 , G11C11/4096 , G11C11/4093 , G11C11/4094
摘要： Semiconductor devices that include circuitry to mitigate unstable or metastable states in logic circuits in response to receipt of an unassigned row address. The semiconductor device may include one or more logic circuits that are configured to adjust particular address-based control signals to mitigate processing based on the unassigned row address. For example, the one or more logic circuits may override processing of the unassigned row address to provide control signals that correspond to an assigned row address, which may allow the semiconductor device to operate in a known state, rather than performing operations based on an unassigned row address.
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公开(公告)号：US20210183422A1
公开(公告)日：2021-06-17
申请号：US17183604
申请日：2021-02-24
IPC分类号： G11C8/08 , G11C29/02 , G11C11/408
摘要： Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
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公开(公告)号：US10672444B1
公开(公告)日：2020-06-02
申请号：US16219671
申请日：2018-12-13
发明人： Satoshi Yamanaka
IPC分类号： G11C8/00 , G11C8/10 , G11C11/408 , G11C8/08
摘要： Provided herein is an apparatus that includes an address output circuit configured to output a first address signal including a plurality of bits including a first bit section and a second bit section, and a decoder circuit configured to decode the first address signal to generate a second address signal. The decoder circuit decides an output value of the second address signal based on the first bit section when a value of the second bit section is in a first value range. The decoder circuit decides the output value of the second address signal regardless of the first bit section when a value of the second bit section is in a second value range.
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公开(公告)号：US20190272866A1
公开(公告)日：2019-09-05
申请号：US16416059
申请日：2019-05-17
发明人： Satoshi Yamanaka , Tetsuaki Okahiro
IPC分类号： G11C11/4091 , G11C11/4074
摘要： Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.
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公开(公告)号：US10242724B2
公开(公告)日：2019-03-26
申请号：US15485696
申请日：2017-04-12
发明人： Satoshi Yamanaka
IPC分类号： G11C8/08 , H03K19/0185 , G11C8/18 , G11C5/14 , G11C11/4076 , G11C11/406 , G11C11/408 , G11C8/10 , H03K19/0175 , G11C8/14 , G11C11/4074
摘要： Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
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公开(公告)号：US09653131B1
公开(公告)日：2017-05-16
申请号：US15043086
申请日：2016-02-12
发明人： Satoshi Yamanaka
IPC分类号： G11C8/08 , H03K19/0185 , G11C8/10 , G11C8/18 , G11C5/14 , G11C11/4076 , G11C11/406
CPC分类号： H03K19/017509 , G11C5/145 , G11C5/147 , G11C8/08 , G11C8/10 , G11C8/14 , G11C8/18 , G11C11/406 , G11C11/4074 , G11C11/4076 , G11C11/4085 , G11C11/4087 , H03K19/018557
摘要： Apparatuses for voltage level control in a semiconductor device are described. An example apparatus includes: a plurality of circuits coupled in parallel between first and second nodes, the first node being supplied with a first voltage; and a voltage supply circuit that supplies the second node with one of second and third voltages, the first voltage being greater than the second voltage, and the second voltage being greater than the third voltage. The plurality of circuits includes a first circuit including a transistor coupled to the second node. The first circuit activates the transistor responsive to a first control signal and further sets a voltage level of the second node higher than the second voltage after the voltage supply circuit supplies the second nodes with the second voltage.
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