Invention Grant
- Patent Title: Method and materials for warpage thermal and interconnect solutions
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Application No.: US15469284Application Date: 2017-03-24
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Publication No.: US10672626B2Publication Date: 2020-06-02
- Inventor: Omkar G. Karhade , Nitin A. Deshpande , Aditya S. Vaidya , Nachiket R. Raravikar , Eric J. Li
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L21/768 ; H01L21/78 ; H01L23/498 ; H01L25/10 ; H01L25/00 ; H01L25/065 ; H01L23/00 ; H01L23/31

Abstract:
Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.
Public/Granted literature
- US20170200621A1 NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS Public/Granted day:2017-07-13
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