A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.