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公开(公告)号：US10243545B2
公开(公告)日：2019-03-26
申请号：US15425277
申请日：2017-02-06
发明人： Beng-Heng Goh , Yi Ren Chin
摘要： Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.
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公开(公告)号：US20180367129A1
公开(公告)日：2018-12-20
申请号：US16113235
申请日：2018-08-27
发明人： Beng-Heng Goh
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.
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公开(公告)号：US20180083606A1
公开(公告)日：2018-03-22
申请号：US15811223
申请日：2017-11-13
发明人： Beng-Heng Goh
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
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公开(公告)号：US20170346470A1
公开(公告)日：2017-11-30
申请号：US15167216
申请日：2016-05-27
发明人： Beng-Heng Goh
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
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公开(公告)号：US10690721B2
公开(公告)日：2020-06-23
申请号：US16128645
申请日：2018-09-12
发明人： Beng-Heng Goh
摘要： A glitch detector includes an input flip-flop clocked by a clock signal and having a non-inverting data output, an inverting data output, and a data input receiving input from the inverting data output, the input flip-flop generating a divided version of the clock signal at the non-inverting data output. A configurable delay chain receives the divided version of the clock signal and generates a delayed version of the divided version of the clock signal as a delay output. An intermediate flip-flop clocked by the clock signal has a data input receiving the delay output, the intermediate flip-flop generating an intermediate output as a function of the delay output. A logic circuit receives the divided version of the clock signal and the intermediate output, and generates a glitch detect signal by performing a logical operation on the divided version of the clock signal and the intermediate output.
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公开(公告)号：US10530348B2
公开(公告)日：2020-01-07
申请号：US16273317
申请日：2019-02-12
发明人： Beng-Heng Goh , Yi Ren Chin
摘要： An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.
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公开(公告)号：US09847778B1
公开(公告)日：2017-12-19
申请号：US15167216
申请日：2016-05-27
发明人： Beng-Heng Goh
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
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公开(公告)号：US10418982B2
公开(公告)日：2019-09-17
申请号：US16113235
申请日：2018-08-27
发明人： Beng-Heng Goh
摘要： A method includes loading a clock divider counter with most significant bits (MSBs) of a divider value, decrementing the counter at a same edge of each pulse of a clock signal, and comparing a value contained in the counter to a reference value and generating an end count signal if the value contained in the counter matches the reference value. If the value is even, the reference value is set to 1. If the value is odd, the reference value is set to 1, except for every other assertion of the end count signal, where the reference value is instead set to 0. A toggle signal transitions at a same edge of each pulse of the end count signal. The counter is reloaded with MSBs of the divider value based upon the end count signal. A divided version of the clock signal is generated based upon the toggle signal.
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公开(公告)号：US10079593B2
公开(公告)日：2018-09-18
申请号：US15811223
申请日：2017-11-13
发明人： Beng-Heng Goh
CPC分类号： H03K5/15033 , H03K23/502 , H03L7/16 , H03L7/183 , H03L7/1974
摘要： A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
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公开(公告)号：US20150015317A1
公开(公告)日：2015-01-15
申请号：US13940713
申请日：2013-07-12
发明人： Beng-Heng Goh
IPC分类号： H03K3/037
CPC分类号： H03K3/037 , G01R31/318541
摘要： Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.
摘要翻译： 用于扫描链配置的可配置触发器单元包括一个或多个多路复用器，触发器和一个或多个逻辑门。 逻辑门可通过不同金属化或半导体层的修改来配置，作为备用栅极运行，或禁止基于触发器单元输出的选择信号在扫描移位和捕捉模式之间切换。 当禁止触发器单元输出时，逻辑门被配置为接收测试信号和数据输入信号，并且基于选择信号选择两者之一传递到触发器。 当用作备用栅极时，逻辑门接收外部输入，并为触发器单元外部的集成电路上的电路提供备用栅极输出。
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