Invention Grant
- Patent Title: Geometry for threshold voltage tuning on semiconductor device
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Application No.: US15993210Application Date: 2018-05-30
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Publication No.: US10692770B2Publication Date: 2020-06-23
- Inventor: Chung-Chiang Wu , Wei-Chin Lee , Shih-Hang Chiu , Chia-Ching Lee , Hsueh Wen Tsau , Cheng-Yen Tsai , Cheng-Lung Hung , Da-Yuan Lee , Ching-Hwanq Su
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8234 ; H01L27/088
Abstract:
Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
Public/Granted literature
- US20190371674A1 Geometry for Threshold Voltage Tuning on Semiconductor Device Public/Granted day:2019-12-05
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