公开(公告)号：US12040235B2

公开(公告)日：2024-07-16

申请号：US17870343

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L21/82345 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US11961732B2

公开(公告)日：2024-04-16

申请号：US17814716

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US20220367263A1

公开(公告)日：2022-11-17

申请号：US17869462

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/78 ,  H01L23/535

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20210391219A1

公开(公告)日：2021-12-16

申请号：US16900439

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L27/088

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US20210043772A1

公开(公告)日：2021-02-11

申请号：US17077383

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Chia-Ching Lee ,  Chung-Chiang Wu ,  Ching-Hwanq Su

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

公开(公告)号：US10170417B2

公开(公告)日：2019-01-01

申请号：US15817281

申请日：2017-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Chiang Wu ,  Chia-Ching Lee ,  Hsueh-Wen Tsau ,  Chun-Yuan Chou ,  Cheng-Yen Tsai ,  Da-Yuan Lee ,  Ming-Hsing Tsai

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/321 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49 ,  H01L23/485

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a metal layer, and a tungsten layer. The dielectric layer is on the substrate and has a recess feature therein. The metal layer is in the recess feature. The metal layer has an oxygen content less than about 0.1 atomic percent. The tungsten layer is in the recess feature and in contact with the metal layer.

公开(公告)号：US20240363627A1

公开(公告)日：2024-10-31

申请号：US18767022

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US12033893B2

公开(公告)日：2024-07-09

申请号：US18359016

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hsueh Wen Tsau ,  Chia-Ching Lee ,  Cheng-Lung Hung ,  Ching-Hwanq Su

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76871 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

公开(公告)号：US20240222108A1

公开(公告)日：2024-07-04

申请号：US18608560

申请日：2024-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Chung-Chiang Wu ,  Shih-Hang Chiu ,  Hsuan-Yu Tung ,  Da-Yuan Lee

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/02175 ,  H01L21/76841 ,  H01L21/76871 ,  H01L27/0886 ,  H01L29/66871

Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.

公开(公告)号：US11735481B2

公开(公告)日：2023-08-22

申请号：US17391220

申请日：2021-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/0234 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.